Designing Logic with AI Support Using Generative VLSI Layouts

Abstract

As the demand for smaller, faster, and more power-efficient integrated circuits (ICs) escalates, the complexity of Very Large-Scale Integration (VLSI) design has surpassed traditional rule-based and manual methodologies. In this context, Artificial Intelligence (AI)-assisted design, particularly using generative models, offers a transformative paradigm in logic circuit layout automation. This paper introduces an AI-driven generative VLSI layout design framework that autonomously creates and optimizes logic circuits through learned design heuristics, layout-space exploration, and power-performance-area (PPA) trade-off modeling. The proposed approach integrates a generative adversarial network (GAN) architecture customized for layout generation, supported by reinforcement learning to fine-tune placement and routing decisions. The generator produces layout proposals conditioned on logic function specifications, while the discriminator evaluates layout legality and efficiency metrics, including wirelength, congestion, and timing closure. Reinforcement signals derived from simulation feedback iteratively refine design rules and geometric configurations. We validated the system on benchmark ISCAS-85 combinational circuits and RISC-V submodules synthesized to 45nm and 28nm process design kits (PDKs). Compared to state-of-the-art electronic design automation (EDA) flows, the AI-generated layouts reduced overall design time by 42%, achieved 17% lower wirelength, and exhibited 11.3% improvement in power-delay product (PDP) on average. The layouts were DRC-clean and met timing without manual intervention in 87% of cases. Our results confirm that AI-driven generative models can intelligently co-optimize functional logic representation and physical layout design, minimizing human effort while pushing the boundaries of silicon efficiency. This work paves the way for self-improving, learning-based VLSI CAD tools that continuously evolve with advancing technology nodes.